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Dual-Phase, Single or Dual Output Synchronous Step-Down Controller
POWER MANAGEMENT Description
The SC2447 is a versatile high-frequency dual phase PWM step-down controller optimized for Philips and Renesas DrMOSTM. Both phases are capable of sourcing or sinking load currents, making the SC2447 suitable for networking system power and DDR applications. The SC2447 employs fixed frequency, continuous-conduction peak current-mode control for easy compensation and fast transient response. The SC2447 can be used to generate two independent outputs (up to 30A per output) or a single 60A output with shared phase current. The PWM signals are 180 out of phase to minimize input/output ripple. Either inductor DC resistance or precision sense resistor can be used for current-mode control. Inductor DC resistance sensing has the advantage of being lossless. Each phase has individual closed-loop soft-start and overload shutdown timer. The SC2447 powers up neatly with pre-biased output. It has tri-state shutdown and hiccup overload protection. In two-phase single-output configuration, the master timer controls the soft-start and overload shutdown functions. The SC2447 is in a lead-free, WEEE and RoHS compliant, TSSOP-28 package.
SC2447
Features
2-Phase Step-down Controller optimized for Philips or Renesas DrMOSTM Out of Phase Operation for Low Input Current Ripple Outputs Source and Sink Current Fixed Frequency Peak Current-Mode Control Lossless Inductor DCR Current Sensing Optional Resistor Current-Sensing for Precise Current-Limit Dual 30A Outputs or 2-Phase 60A Single Output Operation Wide Input Voltage Range: 4.65V to 15V Individual Closed-Loop Soft-Start, Overload Shutdown Timer and Enable Output Voltage as Low as 0.5V Starts into Pre-Bias Output Tri-State PWM Output during Shutdown Programmable Frequency Up to 1MHz Per Phase External Synchronization TSSOP-28 Lead-free Package. Fully WEEE and RoHS Compliant
Applications
Telecommunication Power Supplies DDR Memory Power Supplies Graphic Power Supplies Servers and Base Stations
Typical Application Circuit
VIN 12V CIN1 22F x4 CB1 100nF VDDO CBP L1 1H/1.8m VOUT1 2.5V/20A CO1 100F x3 RFB1A 10K RS1B 22.1K RS1A 22.1K CCS1 100nF RS1C , 11K IN1RFB1B 2.49K CCMP1 10pF COMP1 RA1 24.9K CA1 3.3nF CREF 0.1uF REFOUT REF REFIN SYNC IN2COMP2 ROSC AGND SS1/EN1 SS2/EN2 CSS2 0.1F CSS1 0.1F ROSC , 51.1K RFB2B 7.15K CCMP2 10pF VSSO CBN REG5V VO VI DISABLE VSSC VDDC VDDG C5 1F C3 1F AVCC CVCC 4.7F GDH1 GDL1 GDH2 GDL2 C4 1F C6 1F
R1 10
RVCC 10
R2 10 VDDC VDDG VDDO CBP CBN REG5V VI DISABLE VSSC VSSO RS2A 22.1K VO CB2 100nF
CIN2 22F x4
L2 0.4H/1m RS2B 200K VOUT2 1.2V/25A CO2 100F x3 RFB2A 10K
PIP212-12M CS1+ CS1-
SC2447
CS2+ CS2-
PIP212-12M
CCS2 68nF RS2C , 20K
RA2 16.9K CA2 3.3nF
Figure 1
Revision: December 15, 2006 1
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SC2447
POWER MANAGEMENT Pin Configurations
TOP VIEW
CS1+ CS1ROSC IN1COMP1 SYNC AGND REF REFOUT REFIN COMP2 IN2CS2CS2+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SS1/EN1 NC NC GDH1 GDL1 NC NC GDL2 GDH2 NC NC NC AVCC SS2/EN2
Ordering Information
Device SC2447TSTRT(1)(2) S C 2447E V B Top Mark S C 2447 P ackag e TSSOP-28
Evaluation Board
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices for TSSOP package. (2) Lead free product. This product is fully WEEE and RoHS compliant.
(28 Pin TSSOP)
JA= 84C/W; JC= 13C/W.
Figure 2
Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability.
Parameter Supply Voltage Gate Outputs GDH1, GDH2, GDL1, GDL2 voltages IN1-, IN2- Voltages REFOUT Voltages REF, REFIN Voltage COMP1, COMP2 Voltages CS1+, CS1-, CS2+ and CS2- Voltages SYNC Voltage SS1/EN1 AND SS2/EN2 Voltages Storage Temperature Range Lead Temperature (Soldering) 10 sec Junction Temperature ESD Rating (Human Body Model)
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Symbol AVCC VGDH1, VGDH2,VGDL1, VGDL2 VIN1-,VIN2VREF ,VREFOUT VREFIN VCOMP1,VCOMP2 VCS1+,VCS1-,VCS2+,VCS2VSYNC VSS1,VSS2 TSTG TLEAD TJ ESD
Maximum Ratings -0.3 to 16 -0.3 to 6 -0.3 to AVCC+0.3 -0.3 to 6 -0.3 to AVCC+0.3 -0.3 to AVCC+0.3 -0.3 to AVCC+0.3 -0.3 to AVCC+0.3 -0.3 to 6 -60 to 150 260 150 2
Units V V V V V V V V V C C C kV
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SC2447
POWER MANAGEMENT Recommended Operating Conditions
The performance is not guarantied if exceeding the specifications below.
Parameter AVCC Operating Voltage Ambient temperature Range Junction Temperature Range
Symbol AVCC TA TJ
Conditions
Min 4.65 -40 -40
Typ
Max 15 85 125
Units V C C
Electrical Characteristics
Unless specified: AVCC = 12V, SYNC = 0, ROSC = 51.1k, -40C < TA = TJ < 125C
Parameter Undervoltage Lockout AVCC Start Threshold AVCC Start Hysteresis AVCC Operating Current AVCC Quiescent Current in UVLO Channel 1 Error Amplifier Input Common-Mode Voltage Range(1) Inverting Input Voltage Range(1) Input Offset Voltage Non-Inverting Input Bias Current Inverting Input Bias Current Amplifier Transconductance Amplifier Open-Loop Gain Amplifier Unity Gain Bandwidth(1) Minimum COMP1 Switching Threshold Amplifier Output Sink Current Amplifier Output Source Current Channel 2 Error Amplifier Input Common-mode Voltage Range(1) Inverting Input Voltage Range(1) Input Offset Voltage
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Symbol
Conditions
Min
Typ
Max
Units
AVCCTH AVCCHYST ICC
AVCC Increasing
4.50 0.2
4.65
V V
AVCC= 12V AVCC = AVCCTH - 0.2V
8 2.5
15
mA mA
0 0 0 ~ 70 C IREF IIN1GM1 aOL1 1 -100 -100 170 65 5 V C S 1+ = V C S 1- = 0 VSS1 Increasing VIN1- = 1V, VCOMP1 = 2.5V VIN1- = 0, VCOMP1 = 2.5V 1.7 11 8.5
3 AVCC 3 -250 -250
V V mV nA nA -1 dB MHz V A A
0 0 0 ~ 70 C
3
3 AVCC 1 3
V V mV
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SC2447
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: AVCC = 12V, SYNC = 0, ROSC = 51.1k, -40C < TA = TJ < 125C
Parameter Non-inverting Input Bias Current Inverting Input Bias Current Inverting Input Voltage for 2-Phase Single Output Operation Amplifier Transconductance Amplifier Open-Loop Gain Amplifier Unity Gain Bandwidth(1) Minimum COMP2 Switching Threshold Amplifier Output Sink Current Amplifier Output Source Current Oscillator Channel Frequency Synchronizing Frequency(1) SYNC Input High Voltage SYNC Input Low Voltage SYNC Input Current Channel Maximum Duty Cycle Channel Minimum Duty Cycle Current-limit Comparators Input Common-Mode Range Cycle-by-cycle Peak Current Limit Positive Current-Sense Input Bias Current Negative Current-Sense Input Bias Current PWM Outputs Peak Source Current Peak Sink Current
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Symbol IREFIN IIN2-
Conditions
Min
Typ -100 -150
Max -250 -380
Units nA nA V
2.5 GM2 aOL2 170 65 5 V C S 2+ = V C S 2- = 0 VSS2 Increasing VCOMP2 = 2.5V VCOMP2 = 2.5V 1.7 11 8.5
-1 dB MHz V A A
fCH1, fCH2
0 ~ 70 C
450 2.1fCH 1.5
500
550
kHz kHz V
0.5 ISYNC DMAX1, DMAX2 DMIN1, DMIN2 VSYNC = 0.2V VSYNC = 2V 88 0 1 50
V A % %
0 VILIM1+, VILIM2+ ICS1+, ICS2+ ICS1-, ICS2VCS1- = VCS2- = 0.5V, Sourcing Mode, 0 ~ 70 C V C S 1+ = V C S 1- = 0 V C S 2- = V C S 2- = 0 V C S 1+ = V C S 1- = 0 V C S 2+ = V C S 2- = 0 42.5 50 -0.7 -0.7
AVCC - 1.5 57.5 -2 -2
V mV A A
GDL1, GDL2, GDH1, GDH2 GDL1, GDL2, GDH1, GDH2
4
AVCC = 12V AVCC = 12V
10 8
mA mA
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SC2447
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: AVCC = 12V, SYNC = 0, ROSC = 51.1k, -40C < TA = TJ < 125C
Parameter Output High Voltage Output Low Voltage Maximum Tri-State Leakage Current Propagation delay time from current sense inputs to PWM output(1)
Symbol
Conditions Source IO = 1.2mA, 0 ~ 70 C Sink IO = 1mA GDH in High Impedance State
Min 4.1 0
Typ
Max 5 0.4 2
Units V V A ns
TDLPWM
TA =25 C
85
Soft-Start, Overload Hiccup and Enable Soft-Start Charging Current Overload Hiccup Enabling Voltage Soft-Start Discharging Current at Over Current Condition Overload Hiccup Threshold Voltage Overload Hiccup Recovery Soft-Start Voltage PWM Output Disable SS/EN Voltage PWM Output Enable SS/EN Voltage Internal 0.5V Reference Buffer Output Voltage Load Regulation Line Regulation
Notes: (1) Guaranteed by design, not tested in production.
ISS1, ISS2
VSS1 = VSS2 = 1.5V VSS1 and VSS2 Increasing
9.5 3.2 37 7.5 2.85 0.5 0.6 1.2 1.5
A V A A V V V V
ISS1(DIS), ISS2(DIS)
VIN1-= 0.5VREF,VIN2-= 0.5VREFIN , VSS1 = VSS2 > 2.85V VIN1-= 0.5VREF,VIN2-= 0.5VREFIN , VSS1 = VSS2 < 2.85V VSS1 and VSS2 Decreasing
VSSRCV1, VSSRCV2
VSS1 and VSS2 Decreasing
VREFOUT
IREFOUT = -1mA, 0 C < TA = TJ < 70 C 0 < IREFOUT < -5mA AVCCTH < AVCC < 15V, IREFOUT = -1mA
495
500 0.05
505
mV %/mA
0.02%
%V
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SC2447
POWER MANAGEMENT Typical Performance Characteristics
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SC2447
POWER MANAGEMENT Typical Application Circuit Performance
Circuit Conditions: 2-Output Configuration as in Figure 16. VIN = 12V, VOUT1 = 2.5V, VOUT2 = 1.2V, ROSC = 51.1k, SYNC = 0, and TA = 25C.
Soft-Start Up (VOUT1) Pre-biased Start Up (VOUT1) Shutdown (VOUT1)
VOUT1 1V/div
VOUT1 1V/div
VOUT1 1V/div
VSS1/EN1 2V/div VSS1/EN1 2V/div IOUT1 10A/div
IOUT1 2A/div VSS1/EN1 5V/div
VGDL1 5V/div 10ms/div IOUT1=0A 10ms/div ROUT1=1 200s/div
Output Voltage Ripple (VOUT1)
Load Transient Response (VOUT1)
Overload Hiccup (VOUT1)
VOUT1 20mV/div
VOUT1 0.1V/div
VOUT1 1V/div
IOUT1 10A/div
VSS1/EN1 2V/div
VSW1 10V/div
IOUT1 5A/div
IOUT1 20A/div IOUT1=15A to 20A 200s/div 50ms/div
IOUT1=20A
2s/DIV
Soft-Start Up (VOUT2)
Pre-biased Start Up (VOUT2)
Shutdown (VOUT2)
VOUT2 0.5V/div
VOUT2 0.5V/div
VOUT2 0.5V/div
VSS2/EN2 2V/div
VSS2/EN2 2V/div
IOUT2 1A/div VSS2/EN2 5V/div
IOUT2 20A/div
IOUT2 20A/div VGDL2 5V/div 10ms/div IOUT2=0A 10ms/div ROUT2=1 200s/div
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SC2447
POWER MANAGEMENT Typical Application Circuit Performance
Circuit Conditions: 2-Output Configuration as in Figure 16. VIN = 12V, VOUT1 = 2.5V, VOUT2 = 1.2V, ROSC = 51.1k, SYNC = 0, and TA = 25C.
Output Voltage Ripple (VOUT2) Load Transient Response (VOUT2) Overload Hiccup (VOUT2)
VOUT2 20mV/div
VOUT2 0.1V/div
VOUT2 0.5V/div
VSS2/EN2 2V/div IOUT2 10A/div VSW2 10V/div IOUT2=25A 2s/DIV IOUT2 5A/div IOUT2 20A/div IOUT2=20A to 25A 200s/div 50ms/div
Output Voltage Ripple VOUT1 & VOUT2
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Circuit Conditions: 2-Ouput Configuration, VIN = 12V, LOUT=0.4uH for VOUT= 1.2V, LOUT=1uH for VOUT= 2.5V, 3.3V, and 5.0V, ROSC = 51.1k, and TA = 25C.
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SC2447
POWER MANAGEMENT Typical Application Circuit Performance
Circuit Conditions: 2-Phase Configuration as in Figure 17, VIN = 12V, VOUT = 1.2V, ROSC = 51.1k, SYNC = 0, and TA = 25C.
Soft-Start Up Pre-biased Start Up (VOUT) Shutdown (VOUT)
VOUT 0.5V/div
VOUT 0.5V/div
VOUT 0.5V/div
VSS1/EN1 2V/div
VSS1/EN1 2V/div
IOUT 1A/div VSS1/EN1 5V/div
IOUT 20A/div 10ms/div
IOUT 20A/div IOUT=0A 10ms/div
VGDL1 5V/div ROUT2=1 200s/div
Output Voltage Ripple (VOUT)
Load Transient Response (VOUT)
Overload Hiccup (VOUT)
VOUT 20mV/div VOUT 0.1V/div
VOUT 0.5V/div
IOUT 50A/div VSW1 10V/div VSW2 10V/div IOUT2=50A 1s/DIV
VSS1/EN1 2V/div
IOUT 10A/div
IOUT 50A/div IOUT2=40A to 50A 200s/div 50ms/div

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SC2447
POWER MANAGEMENT Pin Descriptions
Pin 1 2 3 4 5 6 7 8 9 10 11 12 Pin Name Pin Function C S 1+ C S 1ROSC IN1COMP1 SYNC AGND REF REFOUT REFIN COMP2 IN2The Non-inverting Input of Channel 1 Current-sense Amplifier/Comparator The Inverting Input of Channel 1 Current-sense Amplifier/Comparator. Normally tied to the output of the converter. An external resistor connected from this pin to AGND sets the oscillator frequency. Inverting Input of Channel 1 Error Amplifier. Tie an external resistive divider between output 1 and ground for output voltage sensing. The Channel 1 Error Amplifier Output. This pin is used for loop compensation. Edge-triggered Synchronization Input. When not synchronized, tie this pin to a voltage above 1.5V or ground. An external clock (frequency > frequency set with ROSC) at this pin synchronizes the controllers. Analog Signal Ground. The Non-inverting Input of Channel 1 Error Amplifier. Buffered 0.5V internal reference. An external reference voltage is applied to this pin. This is also the non-inverting input of Channel 2 Error amplifier. The Channel 2 Error Amplifier Output. This pin is used for loop compensation. The Inverting Input of Channel 2 Error Amplifier. Tie an external resistive divider between output 2 and ground for output voltage sensing. Tie to AVCC for two-phase single output applications. The Inverting Input of Channel 2 Current-sense Amplifier/Comparator. Normally tied to the output of the converter. The Non-inverting Input of Channel 2 Current-sense Amplifier/Comparator. An external capacitor tied to this pin sets (1) the soft-start time (2) output overload shutdown time for Channel 2. Pulling this pin below 0.6V tri-states GHD2 and forces GDL2 low. Leave open for two-phase single output applications. Power Supply Voltage for the Analog Portion of the Controllers. PWM Output 2. Logic Enable Signal for Channel 2. Logic Enable Signal for Channel 1. PWM Output 1. An external capacitor tied to this pin sets (1) the soft-start time (2) output overload shutdown time for Channel 1. Pulling this pin below 0.6V tri-states GDH1 and forces GDL1 low. No Connection.
13 14 15 16 20 21 24 25 28 17,18,19 22,23,26,27
C S 2C S 2+ SS2/EN2 AVCC GDH2 GDL2 GDL1 GDH1 SS1/EN1 NC
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SC2447
POWER MANAGEMENT Block Diagram
SYNC 6 ROSC 3 COMP1 5 IN1 4 REF 8 OSCILLATOR
CLK2 CLK FREQUENCY DIVIDER SLOPE COMP. 0.5V CLK1 1.25V REFERENCE
AVCC 16
GDH1 25
REFSS1
SLOPE2 EA1
+ +
SLOPE1
R Q S TGON1 UV
TRI-STATE1
PWM1
+ +
CLK1
CS1+ 1 CS12
+ ISEN1
+
+ ILIM1+
GDL1 24
OC1
50mV SSL1
PRE-BIAS SOFT-START & OVERLOAD HICCUP CONTROL 1
OL1 DSBL1 SS1/EN1 SS1/EN1 1.25V 28
0.5V 2R REFOUT 9
COMP2 11 2.5V SEL B CLK2 ANALOG SWITCH EA2 Y A MUX
+
IN2 12 REFIN 10
REFSS2
+ +
CS2+ 14 CS213
+
-
ISEN2
50mV
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SLOPE2 R Q S TGON2 UV PWM2
+
R UVLO 4.3/4.5V AGND 7 GDH2 20 TRI-STATE2
+
+
+
CLK2 PRE-BIAS SOFT-START & OVERLOAD HICCUP CONTROL 2
OL2 DSBL2
GDL2 21
+
-
ILIM2+
OC2 SSL2
SS2/EN2 SS2/EN2 R 2R 1.25V 15
REFSS2
Figure 3. SC2447 Block Diagram
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SC2447
POWER MANAGEMENT Block Diagram
2.85V
+
0.5V/3.2V 9.5uA SS/EN R COMP SSL S Q OL
+
0.8V
(0.6V min.)
S Q R R DSBL
17.0uA UV 46.5uA Q S
TGON CLK OC
Figure 4. Soft-Start and Overload Hiccup Control Circuit
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SC2447
POWER MANAGEMENT Timing Chart
AVCC 4.5V VSS/EN
Enable Hiccup
AVCC 4.5V VSS/EN
Enable Hiccup
3.2V
3.2V
VCOMP 1.5V 1.25V
1.25V 1.5V
VCOMP
0
0
0.5V (VREF)
VREFSS VIN-
0.5V (VREF)
VREFSS VIN-
0 0 GDH in high impedance state 0
0
GDH GDL t2 t4 t5 t6 t7
0 GDH in high impedance state 0
GDH GDL t0 t1 t2 t3t4 t5 t6 t7
t0
t1
(a) Normal Start Up
(b) Pre-Biased Start Up
Figure 5. SC2447 Start-up Timing Diagram
AVCC
4.3V VSS/EN VCOMP
VREFSS VIN-
0.5V (VREF)
GDH GDL t16 t17
GDH in high impedance state
Figure 6. SC2447 UVLO Shutdown Timing Diagram
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SC2447
POWER MANAGEMENT Timing Chart
VSS/EN 3.2V
Enable Hiccup Enable Hiccup
2.85V VCOMP
1.50V 1.25V 0.8V 0.5V 0V 0.5V
Reference Voltage Min.(VREF, VREFSS)
VIN-
0V
GDH i n high impedance state
GDH
0V
GDL
0V
t7
t8
t9
t10 t11 t12
t13
t14
t15
Figure 7. SC2447 Overload Hiccup Operation Timing Diagram
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SC2447
POWER MANAGEMENT Application Information
The SC2447 consists of two current-mode synchronous buck controllers with many integrated functions. The SC2447 can be used to generate: 1) two independent outputs from a common input or two different inputs or, 2) dual-phase output with current sharing, 3) current sourcing/sinking from common or separate inputs as in DDR (I and II) memory application. Step-Down Converter Starting from the following step-down converter specifications, Input voltage range: Vin [ Vin,min , Vin,max ] Input voltage ripple (peak-to-peak): Vin Output voltage: Vo Output voltage accuracy: Output voltage ripple (peak-to-peak): Vo Nominal output (load) current: Io Maximum output current limit: Io,max Output (load) current transient slew rate: dIo (A/s) Circuit efficiency: Selection criteria and design procedures for the following are described. 1) 2) 3) 4) 5) 6) 7) output inductor (L) type and value output capacitor (Co) type and value input capacitor (Cin) type and value power MOSFETs current sensing and limiting circuit voltage sensing circuit loop compensation network In the SC2447, the falling edge of the clock turns on the top MOSFET. The inductor current and the sensed voltage ramp up. After the sensed voltage crosses a threshold determined by the error amplifier output, the top MOSFET is turned off. The propagation delay time from the turnon of the controlling FET to its turn-off is the minimum switch on time. This propagation delay time consists of the propagation delay time (TDLPWM) from the current sense inputs to the PWM output and the propagation delay time (TDLTG) from the trailing edge of the PWM input to the trailing edge of the phase voltage. The SC2447 has a typical propagation delay time from the current sense inputs to the PWM output of about 85ns at room temperature. The shortest on interval (TMINON) of the controlling FET is then 85ns+TDLTG. Assuming that TDLTG is 45ns, the controller either does not turn on the top MOSFET at all or turns it on for at least 130ns. TDLTG can be found in the MOSFET driver datasheet. For a synchronous step-down converter, the operating duty cycle is VO/VIN. The required on time for the top MOSFET is VO/(VIN*fs). If the frequency is set such that the required pulse width is less than 130ns, assuming TDLTG is 45ns, then the converter will start skipping cycles. Due to minimum on-time limitation, simultaneously operating at very high switching frequency and very short duty cycle is not practical. If the voltage conversion ratio VO/VIN and hence the required duty cycle is higher, the switching frequency can be increased to reduce the size of passive components. There will not be enough modulating headroom if the on time is made equal to the minimum on time (TMINON). For ease of control, set the switching frequency so that the pulse width is at least 1.5 times the minimum on time. For a given output power, the size of the passive components are inversely proportional to the switching frequency, whereas MOSFET/Diode switching losses are proportional to the operating frequency. Other issues such as heat dissipation, packaging and the cost issues are also considered. The frequency bands for signal transmission should be avoided because of EM interference. Minimum Switch On Time Consideration
Operating Frequency (fs) The switching frequency in the SC2447 is userprogrammable. The advantages of using constant frequency operation are simple passive component selection and ease of feedback compensation. Before setting the operating frequency, the following trade-offs should be considered: 1) Passive component size 2) Efficiency 3) EMI condition 4) Minimum switch on time 5) Maximum duty ratio
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SC2447
POWER MANAGEMENT Application Information (Cont.)
Setting the Switching Frequency
The switching frequency is set with an external resistor connected from Pin 3 to the ground. The set frequency is inversely proportional to the resistor value (Figure 8). Consider the following when choosing inductors: a) Inductor core material: For high efficiency applications above 350kHz, ferrite, Kool-Mu and polypermalloy materials should be used. Low-cost powdered iron cores can be used for cost sensitive-applications below 350kHz but with attendant higher core losses. b) Select inductance value: Sometimes the calculated inductance value is not available off-the-shelf. The designer can choose the next larger standard inductance value. The inductance varies with temperature and DC current. It is a good engineering practice to re-evaluate the resulting current ripple at the rated DC output current. c) Current rating: The saturation current of the inductor should be at least 1.5 times of the peak inductor current under all conditions. Output Capacitor (Co) and Vout Ripple Figure 8. Free Running Frequency vs. ROSC Inductor (L) and Ripple Current Both step-down controllers in the SC2447 operate in synchronous continuous-conduction mode (CCM) regardless of the output load. The output inductor selection/design is based on the output DC and transient requirements. Both output current and voltage ripples are reduced with larger inductors but it takes longer to change the inductor current during load transients. Conversely, smaller inductors results in lower DC copper losses but the AC core losses (flux swing) and the winding AC resistance losses are higher. A compromise is to choose the inductance such that peak-to-peak inductor ripple-current is 20% to 30% of the rated output load current. Assuming that the inductor current ripple (peak-to-peak) value is *Io, the inductance value will then be
V (1 - D) . L= o I o f s
800 700 600 fs (kHz) 500 400 300 200 100 0 0 50 100 150 200 250 Rosc (k Ohm)
The output capacitor filters the inductor current in the steady state and serves as a reservoir during load transient. The output capacitor can be modeled as an ideal capacitor in series with its parasitic ESR (Resr) and ESL (Lesl) (Figure 9 ).
Co
Lesl
Resr
Figure 9. An Equivalent Circuit of Co If the current through the branch is ib(t), the voltage across the terminals will then be
vo (t ) = Vo +
dib (t ) 1 ib (t )dt + Lesl dt + Resrib (t ). Co 0
t
The peak current in the inductor becomes (1+/2)*Io and the RMS current is
I L,rms = I o 1 +
(c) 2006 Semtech Corp.
This basic equation illustrates the effect of ESR, ESL and Co on the output voltage. The first term is the DC voltage across Co at time t=0. The second term is the voltage variation caused by the
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2
12
.
SC2447
POWER MANAGEMENT Application Information (Cont.)
charge balance between the load and the converter output. The third term is voltage ripple due to ESL and the fourth term is the voltage ripple due to ESR. The total output voltage ripple is then the vector sum of the last three terms. Since the inductor current waveform is a triangular with peak-to-peak value *Io, the ripple-voltage caused by inductor current ripple is
v C Io , 8C o fs
The voltage rating of aluminum capacitors should be at least 1.5Vo. The RMS current ripple rating should also be greater than
Io 23 .
the ripple-voltage due to ESL is
v ESL = L esl fs Io , D
Usually it is necessary to have several capacitors of the same type in parallel to satisfy the ESR requirement. The voltage ripple cause by the capacitor charge/discharge should be an order of magnitude smaller than the voltage ripple caused by the ESR. To guarantee this, the capacitance should satisfy
Co > 10 . 2fsR esr
and the ESR ripple-voltage is
v ESR = R esr Io .
Aluminum capacitors (e.g. electrolytic, solid OS-CON, POSCAP, tantalum) have high capacitances and low ESLs. The ESR has the dominant effect on the output ripple voltage. It is therefore very important to minimize the ESR. When determining the ESR value, both the steady state ripple-voltage and the dynamic load transient need to be considered. To keep the steady state output ripplevoltage < Vo, the ESR should satisfy
R esr1 < Vo . Io
In many applications, several low ESR ceramic capacitors are added in parallel with the aluminum capacitors in order to further reduce ESR and improve high frequency decoupling. Because the values of capacitance and ESR are usually different in ceramic and aluminum capacitors, the following remarks are made to clarify some practical issues. Remark 1: High frequency ceramic capacitors may not carry most of the ripple current. It also depends on the capacitor value. Only when the capacitor value is set properly, the effect of ceramic capacitor low ESR starts to be significant. For example, if a 10F, 4m ceramic capacitor is connected in parallel with 2x1500F, 90m electrolytic capacitors, the ripple current in the ceramic capacitor is only about 42% of the current in the electrolytic capacitors at the ripple frequency. If a 100F, 2m ceramic capacitor is used, the ripple current in the ceramic capacitor will be about 4.2 times of that in the electrolytic capacitors. When two 100F, 2m ceramic capacitors are used, the current ratio increases to 8.3. In this case most of the ripple current flows in the ceramic decoupling capacitor. The ESR of the ceramic capacitors will then determine the output ripple-voltage. Remark 2: The total equivalent capacitance of the filter bank is not simply the sum of all the paralleled capacitors. The total equivalent ESR is not simply the parallel combination of all the individual ESRs either. Instead
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To limit the dynamic output voltage overshoot/ undershoot to within (say 3%) of the steady state output voltage) from no load to full load, the ESR value should satisfy
R esr 2 < Vo . Io
Then, the required ESR value of the output capacitors should be Resr = min{Resr1,Resr2 }.
(c) 2006 Semtech Corp.
SC2447
POWER MANAGEMENT Application Information (Cont.)
they should be calculated using the following formulae.
C eq () := (R1a + R1b )2 2C1a C1b + (C1a + C1b )2
2 2
(R1a C1a + R1b C1b )2 C1a C1b + (C1a + C1b )
2 2
R eq () :=
R1aR1b (R1a + R1b )2C1a C1b + (R1b C1b + R1a C1a )
2 2 2 2
(R1a + R1b )2 2 C1a C1b + (C1a + C1b )2
2 2
where R 1a and C 1a are the ESR and capacitance of electrolytic capacitors, and R1b and C1b are the ESR and capacitance of the ceramic capacitors respectively. (Figure 10)
Figure 11. A Simple Model for the Converter Input
C1a
C1b
Ceq
R1a
R1b
Req
Figure 10. Equivalent RC Branch Req and Ceq are both functions of frequency. For rigorous design, the equivalent ESR should be evaluated at the ripple frequency for voltage ripple calculation when both ceramic and electrolytic capacitors are used. If R1a = R1b = R1 and C1a = C1b = C1, then Req and Ceq will be frequencyindependent and Req = 1/2 R1 and Ceq = 2C1. Input Capacitor (Cin) The input supply to the converter usually comes from a pre-regulator. Since the input supply is not ideal, input capacitors are needed to filter the current pulses at the switching frequency. A simple buck converter is shown in Figure 11. In Figure 11 the DC input power supply has an internal impedance Rin and the input capacitor Cin has an ESR of R esr . The MOSFET and the input capacitor current waveforms, the ESR voltage ripple and the input voltage ripple are shown in Figure 12. Figure 12. Typical Waveforms at Converter Input It can be seen that high di/dt pulse current flows in the input capacitor. Capacitors with low ESL should be used. It is also important to place the input capacitor close to the MOSFETs on the PC board to reduce trace inductance around the pulse current loop. The RMS value of the capacitor current is approximately
ICin = Io D[(1+
2
12
D D )(1- )2 + 2 (1- D) ].
The power dissipated in the input capacitor is then PCin = ICin2Resr.
(c) 2006 Semtech Corp.
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SC2447
POWER MANAGEMENT Application Information (Cont.)
For reliable operation, the maximum power dissipation in the capacitors should not result in more than 10oC of temperature rise. Many manufacturers specify the maximum allowable ripple current (ARMS), rating of the capacitor at a given ripple frequency and ambient temperature. The input capacitance should be large enough to handle the ripple current. For higher power applications, multiple capacitors are placed in parallel to increase the ripple current handling capability. Sometimes meeting tight input voltage ripple specifications may require the use of larger input capacitance. At full load, the peak-to-peak input voltage ripple due to the ESR is
v ESR = Resr (1 + ) I o . 2
If D1<0.5 and D2<0.5, then
I Cin D1I o1 + D2 I o2 .
2 2
Choosing Power MOSFETs Power MOSFETs with integrated gate drivers such as PIP212, R2J20601NP, PIP202, PIP201 and IP2001, IP2002 are suitable for SC2447 application. Current Sensing Inductor current sensing is required for the current-mode control. Although the inductor current can be sensed with a precision resistor in series with the inductor, the lossless inductive current sense technique can be used in the SC2447. This technique has the advantages of, 1) lossless current sensing 2) lower cost compared to resistive sensing 3) more accurate compared to RDS(ON) sensing The basic arrangement of the inductive current sense is shown in Figure 13. RL is the equivalent series resistance of the output inductor. Rs and Cs form a RC network for inductor current sensing.
Vin
Q1 iL(t) Cin L Rs Q2 vC(t) RL Cs
The peak-to-peak input voltage ripple due to the capacitor is
vC DI o , Cin f s
From these two expressions, CIN can be found to meet the input voltage ripple specification. In a multi-phase converter, interleaved switching reduces ripple. The two step-down channels of the SC2447 operate at 180 degrees from each other. If both step-down channels in the SC2447 are connected in parallel, both the input and the output RMS currents will be reduced. Ripple cancellation effect of interleaving allows the use of smaller input capacitors. When converter outputs are connected in parallel and interleaved, a smaller inductor and capacitor can be used for each channel. The total output ripple-voltage remains unchanged. The use of a smaller inductor helps speed up the output load transient. When two channels with a common input are interleaved, the combined input current waveform depends on the duty ratios and the output currents of both channels. Assuming that the output current ripple is small, the following formula can be used to estimate the RMS ripple current in the input capacitor. Let the duty ratio and output current of Channel 1 and Channel 2 be D1, D2 and Io1, Io2, respectively.
Vo
Cout Rload
Figure 13. The Basic Structure of Inductive Current Sense In steady state, the DC voltage across RL is VCS = RL IO . Notice that the DC value of VCs is independent of the values of L, Rs and Cs. This means that, if only the average load current information is needed (such as in
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(c) 2006 Semtech Corp.
SC2447
POWER MANAGEMENT Application Information (Cont.)
average current mode control), this current sensing method is sufficient without time constant matching requirement. In the current mode control as implemented in SC2447, voltage ripple on Cs is required for PWM operation. In fact, the VCs AC peak-to-peak voltage ripple (denoted as VCs) directly affects the signal-to-noise ratio of the PWM operation. In general, smaller VCs leads to lower signalto-noise ratio and more noise sensitive operation. Larger V Cs leads to more circuit (power stage) parameter sensitive operation. A good engineering compromise is: of 22nF ~ 330nF. a) When the required current limit ILM is higher than ILMcp, Rs3 is not needed and solve the following three equations for Rs, Rs1, and Rs2:
( Rs // Rs1 ) Cs = I LM RL L , RL
Rs1 = 50mV , Rs + Rs1
VCs~ RL Io.
It is necessary to match the following time constants to equalize the ripple.
and
R s 2 = R s // R s1 .
Note that RS2 is made equal to RS//RS1 to reduce effect of the bias current of the current amplifier in SC2447. b) When the required current limit ILM is less than ILMcp, remove Rs1 and solve the following two equations for Rs and Rs3:
RsCs = L , RL
L Rs C s . RL
For example, L = 1H and RL = 1.8m, the time constant RsCs should be set to 555.6s. If one selects Cs = 33nF, then Rs = 16.9 k. Scaling the Current Limit Over-current is handled differently in the SC2447 depending on the direction of the inductor current. If the differential sense voltage between CS+ and CSexceeds +50mV, the PWM signal (GDH) will go low. The MOSFET driver will turn off the top MOSFET and turn on the bottom MOSFET, to limit the inductor current. This +50mV is the cycle-by-cycle peak current limit when the load is drawing current from the converter. There is no cycle-by-cycle current limit when the inductor current flows in the reverse direction. In the circuit of Figure 13, the equivalent inductor current limit is set according to
I LMcp 50mV = , RL
I LM RL +
Rs VO = 50mV , Rs 3
Rs2 is then calculated from
Rs 2 = Rs 3 Rs . Rs 3 - Rs
Vin
Q1 Vgs1 iL(t) PN Cin Rs Q2 Vgs2 vC(t) Rs1 L RL
Vo
Cs Cout Rload
when the load is sourcing current from the converter. If RL = 1.8m, then ILMcp = 27.8A. The circuit in Figure 14 allows the user to scale the equivalent current limit with the same RL. CS in the current sensing network is usually in the range
(c) 2006 Semtech Corp. 20
+ ISEN -
1 2
Rs2 Rs3
Figure 14. Scaling the Equivalent Current Limit
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SC2447
POWER MANAGEMENT Application Information (Cont.)
Overload Protection and Hiccup During start-up, the capacitor from the SS/EN pin to ground functions as a soft-start capacitor. After the converter starts and enters regulation, the same capacitor operates as an overload shutoff timing capacitor. There is an internal net 9.5A current source charging the soft start capacitor C32(C33), connected to the SS/EN pin. The soft-start voltage VSS/EN will reach its final value if no current limit occurs. As the load current increases, the cycle-by-cycle current-limit comparator will first limit the inductor current. If VSS/EN is higher than 3.2V, an internal net 37A current source will discharge the soft-start capacitor C32(C33) during the off time after tripping the over-current comparator. If VSS/EN falls to 2.85V, the controller will shut off both the top and the bottom MOSFETs by pulling down the GDL and tri-stating the GDH output (PWM). An internal net 7.5A current source discharges C32(C33) . When the capacitor is discharged below 0.5V, the overload hiccup latch is reset, the 9.5A current source recharges the SS/EN capacitor and converter restarts. The overload hiccup function is enabled when the soft start capacitor voltage exceeds 3.2V. The converter will repeatedly start and shut off until it is no longer overloaded when the soft-start voltage exceeds 3.2V. This hiccup mode of overload protection is a form of foldback current limiting. The following calculations estimate the average inductor current when the converter output is shorted to the ground: a) The time taken to discharge the capacitor from 3.2V to 2.85V is
t ssf 1 = C32 (3.2 - 2.85)V . 37 A
When C32 = 0.1F, tssr is calculated as 28.4ms. Note that during soft start, the converter only starts switching when the voltage at SS/EN exceeds 1.25V. d) The effective start-up time is
t sso = C32 (3.2 - 1.25)V . 9.5A
The average inductor current is then
I Leff = I LMcp t sso t ssf 1 + t ssf 2 + t ssr .
ILeff 0.34 ILMcp and is independent of the soft start capacitor value. The converter will not overheat in hiccup. Setting the Output Voltage The non-inverting inputs of channel 1 and channel 2 error amplifiers are brought out as device pins (Pin 10 and Pin 8). These pins can be tied to the precision 0.5V reference output (Pin 9) of the SC2447. A simple voltage divider (Ro1 at top and Ro2 at bottom) sets the converter output voltage. The voltage feedback gain h=0.5/Vo is related to the divider resistors as follows:
Ro 2 =
h Ro1 . 1- h
If C32 = 0.1F, tssf1 is calculated as 0.945ms. b) The time taken to discharge the capacitor from 2.85V to 0.5V is
t ssf 2 = C32 ( 2.85 - 0.5)V . 7.5A
Once either R o1 or R o2 is chosen, the other can be calculated for the desired output voltage Vo. Since the number of standard resistance values is limited, the calculated resistance may not be available as a standard value resistor. As a result, there will be a set error in the converter output voltage. This non-random error is caused by the feedback voltage divider ratio. It cannot be corrected by the feedback loop. The following table lists a few standard resistor combinations for realizing some commonly used output voltages.
Vo (V) (1- h)/h 0.6 0.2 200 1K 0.9 0.8 806 1K 1.2 1.4 1.4K 1K 1.5 2 2.0K 1K 1.8 2.6 2.61K 1K 2.5 4 4.02K 1K 3.3 5.6 5.62K 1K
If C32 = 0.1F, tssf2 is calculated as 31.3ms. c) The soft start time from 0.5V to 3.2V is
t ssr
(c) 2006 Semtech Corp.
Ro1 (Ohm) Ro2 (Ohm)
(3.2 - 0.5)V = C32 . 9.5A
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SC2447
POWER MANAGEMENT Application Information (Cont.)
Only the voltages in boldface can be precisely set with standard 1% resistors. From this table, one may also observe that when the value The slope of the compensation ramp is then S e=0.4*fs. The slope of the internal compensation ramp is well above the minimal slope requirement for current loop stability and is sufficient for all the applications. With the inner current loop stable, the output voltage is then regulated with the outer voltage feedback loop. A simplified equivalent circuit model of the synchronous Buck converter with current mode control is shown in Figure 15.
1 - h Vo - 0.5 = . 0.5 h
and its multiples fall into the standard resistor value chart (1%, 5% or so), it is possible to use standard value resistors to set up the exact and required output voltage value. The input bias current of the error amplifier also causes an error in setting the output voltage. The maximum inverting input bias current of the error amplifiers is 380nA. Assuming the non-inverting input is tied to the 0.5V reference output, the percentage error in the second output voltage will be -100% * (0.38A) * RR /[0.5 * (R +R ) ]. To keep this error below o1 o2 o1 o2 0.2%, R < 2.6k. o2 Loop Compensation SC2447 uses current-mode control for both step-down channels. Current-mode control is a dual-loop control system in which the inductor peak current is loosely controlled by the inner current-loop. The higher gain outer loop regulates the output voltage. Since the current loop makes the inductor appear as a current source, the complex high-Q poles of the output LC network are split into a dominant pole determined by the output capacitor and the load resistance and a high frequency pole. This polesplitting property of current-mode control greatly simplifies loop compensation. The inner current-loop is unstable (sub-harmonic oscillation) unless the inductor current up-slope is steeper than the inductor current down-slope. For stable operation above 50% duty-cycle, a compensation ramp is added to the sensed-current. In the SC2447 the compensation ramp is approximately Vramp=D*0.4V.
k
Figure 15. A Simple Model of Synchronous Buck Converter with Current Mode Control The transconductance error amplifier (in the SC2447) has a gain gm of 170A/V. The target of the compensation design is to select the compensation network consisting of C2, C3 and R2, along with the feedback resistors Ro1, Ro2 and the current sensing gain, such that the converter output voltage is regulated with satisfactory dynamic performance.
(c) 2006 Semtech Corp.
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SC2447
POWER MANAGEMENT Application Information (Cont.)
PC Board Layout Issues Circuit board layout is very important for the proper operation of high frequency switching power converters. A power ground plane is required to reduce ground bounces. The followings are suggested for proper layout. Power Stage 1) Separate the power ground from the signal ground. In the SC2447, the power ground PGND should be tied to the source terminal of lower MOSFETs. The signal ground AGND should be tied to the negative terminal of the output capacitor. 2) Minimize the size of high pulse current loop. Place the top MOSFET, bottom MOSFET and the input capacitors close to each other with short and wide traces. In addition to the aluminum energy storage capacitors, add multi-layer ceramic (MLC) capacitors from the input to the power ground to improve high frequency bypass. Control Section 1) The frequency-setting resistor ROSC should be placed close to Pin 3. Trace length from this resistor to the analog ground should be minimized. 2) Solder the bias decoupling capacitor right across the AVCC and analog ground AGND. 3) Place the current sensing network away from the power circuit and close to the corresponding CS+ and CS- pins. Use X7R ceramic capacitor for the sensing capacitor because of its temperature stability. 4) Use an isolated local ground plane for the controller and tie it to the negative side of output capacitor bank.
(c) 2006 Semtech Corp.
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VIN (12V)
C5 C4 22uF 22uF 22uF R23 22uF 10 D15 3.3V C3 C2
M1
4 VDDC VDDG REG5V CBN L1 1uH/1.8mOhm 56 VI C14 2.2nF R6 C21 C22 100uF R11 10K 100uF 100uF C46 C49 C30 10uF x 2 RCS+1 C50 22pF 22.1K RCS-1 100nF 22.1K VSSO R13 2.2 VO C48 1uF 55 2 DISABLE VDDG_EN VSSC 10 C38 100nF CBP 5 VDDO 3
(c) 2006 Semtech Corp.
C19 1uF C52 1uF 54
VO1 (2.5V, 20A)
EN1
D17 1N4148
U1
CS1+ CS1Rosc IN1COMP1 SYNC AGND REF REFOUT C10 C9 22uF 22uF 22uF R24 22uF 10 C8 C7 REFIN COMP2 IN24 VDDC VDDG REG5V CBN 56 VI C15 2.2nF VSSO R14 2.2 VO R5 22.1K RCS+2 C51 22pF 200K RCS-2 20K C41 100pF R17 7.15K C44 1uF R12 10K C20 68nF C26 100uF C27 100uF C47 100uF 55 2 DISABLE VDDG_EN VSSC 10 C39 100nF L2 0.4uH/1mOhm CBP 5 VDDO 3 C18 1uF C53 1uF 54 C36 10pF CS2CS2+ C37 3.3nF 14 13 12 R21 16.9K 11 D16 3.3V 10 9 C20 0.1uF C31 3.3nF 8 C28 10pF 7 6 R19 24.9K 5 C43 1uF 4 51.1K R16 2.49K C42 100pF 3 R5 11K 2 1
PIP212-12M
28
SS1/EN1
POWER MANAGEMENT Typical Application Schematic
C32 0.1uF
27
NC
26
NC
25
GDH1
24
GDL1
23
NC
22
VIN (12V)
NC
21
GDL2
20
GDH2
19
NC
EN2
18
NC
17
24
PIP212-12M
D18
NC
M2
16
1N4148
AVCC
15
SS2/EN2
C33 0.1uF
SC2447
VO2 (1.2V, 25A)
C25 10uF x 2 C24 1uF
R26
10
C35 4.7uF
VIN= 12V VOUT= 2.5V/20A, 1.2V/25A Switching Frequency= 500kHz M1,M2: Philips PIP212-12M L1, L2: Delta SPL146 Type Power Inductor Input Capacitors: Murata GRM31CR61C226K (22uF/16V) Output Capacitors: TDK C3225X5R0J107K (100uF/6.3V) Murata GRM31CR60J106K (10uF/6.3V)
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SC2447
Figure 16. SC2447/PIP212 Two Outputs Application
VIN (12V)
C5 C4 22uF 22uF 22uF R23 22uF 10 D15 3.3V C3 C2
(c) 2006 Semtech Corp.
M1
4 VDDC VDDG REG5V CBN L1 0.4uH/1mOhm 56 VI C14 2.2nF R6 C21 RCS+1 C50 22pF 1 2 3 4 5 6 7 8 9 10 11 10 12 4 13 3 14 54 REG5V CBN 56 VI C15 2.2nF VSSO R14 2.2 VO R5 20K RCS+2 C51 22pF 2.2M RCS-2 20K C41 R17 10K R18 2.2M 100pF C20 68nF 55 2 DISABLE VDDG_EN VSSC 10 C53 1uF C39 100nF L2 0.4uH/1mOhm VDDG CBP C18 1uF 5 VDDC VDDO R24 22uF 22uF 22uF 22uF D16 3.3V C31 3.3nF C10 C9 C8 C7 C20 0.1uF C28 10pF R16 7.15K C26 100uF C47 100uF C48 100uF C27 C22 10uF x 2 1uF x 2 R19 9.31K C43 1uF R11 10K R15 2.2M 51.1K C42 100pF R5 20K C24 100uF C67 470pF C46 100uF C49 100uF C30 10uF x 2 RCS-1 2.2M 68nF 20K VSSO R13 2.2 DISABLE VDDG_EN VSSC VO 55 2 10 C38 100nF CBP 5 VDDO 3 C19 1uF C52 1uF 54
EN
D17
1N4148
U1
PIP212-12M
POWER MANAGEMENT Typical Application Schematic
28
VO2 (1.2V, 50A)
SS1/EN1
CS1+
C32 0.1uF
27
NC
CS1-
26
NC
Rosc
25
GDH1
IN1-
24
GDL1
COMP1
23
NC
SYNC
22
VIN (12V)
NC
AGND
21
GDL2
REF
20
GDH2
REFOUT
19
NC
REFIN
25
M2 PIP212-12M
R27 10K C44 1uF
18
NC
COMP2
17
NC
IN2-
16
AVCC
CS2-
15
SS2/EN2
CS2+
SC2447
R26
10
C35 4.7uF
VIN= 12V VOUT= 1.2V/50A Switching Frequency= 500kHz M1,M2: Philips PIP212-12M L1, L2: Delta SPL146 Type Power Inductor Input Capacitors: Murata GRM31CR61C226K (22uF/16V) Output Capacitors: TDK C3225X5R0J107K (100uF/6.3V) Murata GRM31CR60J106K (10uF/6.3V)
SC2447
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Figure 17. SC2447/PIP212 Dual-Phase Single Output Application
SC2447
POWER MANAGEMENT Outline Drawing - TSSOP-28
A e N 2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 123 e/2 B D A2 A C bxN bbb A1 C A-B D GAGE PLANE 0.25 L (L1) DETAIL H c E D
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
DIMENSIONS MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX
.047 .002 .006 .031 .042 .007 .012 .003 .007 .378 .382 .386 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 28 8 0 .004 .004 .008 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 9.60 9.70 9.80 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 28 0 8 0.10 0.10 0.20
aaa C SEATING PLANE
01
SIDE VIEW
SEE DETAIL
A
A
NOTES: 1. 2. 3. 4. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -HDIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. REFERENCE JEDEC STD MO-153, VARIATION AE.
Land Pattern - TSSOP-28
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
(c) 2006 Semtech Corp. 26 www.semtech.com

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